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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADSP-2141L one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 dsp applications security coprocessor for high speed networking prod- ucts (routers, switches, hubs) cryptographic core for firewalls, hardware encryptors, and more crypto peripheral for implementing secure nic adapt- ers (10/100 ethernet, token ring, isdn) secure modem-on-a-chip (v.34, adsl) features des crypto block 640 mbps sustained performancesingle des 214 mbps sustained performancetriple des supports all modes: ecb; cbc; 64-bit ofb; and 1-, 8-, 64-bit cfb. includes automatic padding implements ipsec esp transforms autonomously at oc-3 (155 mbps) rates (3-des, sha-1) hash block hardware-based sha-1 and md-5 hashing 253 mbps sustained performancesha-1 315 mbps sustained performancemd-5 implements ipsec ah and hmac transforms secure kernel control tamper-resistant isolation of cryptographic functions enforces security perimeter around crypto functions and crypto storage locations anticloning protection secure algorithm download safenet cgx library on-chip safenet cgx crypto library with flexible cgx api includes chained and parallel execution commands such as hash-and-encrypt embodied as 32k words (32k 3 24) kernel program mask-programmed into on-chip rom on-chip protected 4k 3 16 security scratchpad ram random number generator hardware-based nondeterministic random number generator generates internal session keys that are never exposed outside of the safenet dsp redundant fail-safe design up to 1.3 mbits of random data available per second functional block diagram bus_mode idma mode pci mode idma bus interrupts flags sport 0 serial ports sport 1 protected kernel ram (4k 3 16) 32 external memory interface rng block public key accelerator 32-bits data 26-bits addr laser variable store serial eeprom interface interrupt controller application registers ram/rom pf7/ int_h dma-32 controller idma interface 16 pci or cardbus interface 32 16 bus_mode bus_sel 16- or 32-bit bus kernel mode control kernel rom 32k 3 24 prog rom 16k 3 24 data rom 16k 3 16 timer adsp-218x dsp core emi bus encrypt block (des, 3-des) hash block (md-5, sha-1) safenet is a registered trademark of information resource engineering (ire). r
rev. 0 ADSP-2141L C2C public key accelerator accelerator for math-intensive public key operations diffie-hellman negotiate: <29 ms (1024-bit modulus, 180-bit exponent) rsa 1024-bit sign: <29 ms; rsa 1024-bit verify: 6 ms dsa sign: <39 ms; dsa verify: <66 ms key management block laser-programmed unique triple-des cryptovariable protects off-chip storage support for secure storage of both secret keys and public/private key pairs trust-model rules enforcement only encrypted keys may be exported off the chip internal key cache for 15 keyscan be expanded to 700 keys on-chip keys may also be securely stored off-chip, allowing unlimited storage dsp core 40 mips sustained performance single-cycle instruction execution single-cycle context switch zero-overhead looping low power dissipation 16k words (16k 3 24) on-chip program ram 16k words (16k 3 16) on-chip data ram 64m words off-chip program and data memory programmable 16-bit interval timer with prescale pci bus/cardbus interface 32-bit 3.3 v bus interface 33 mhz or 40 mhz* bus speed bus master and target modes can directly dma between crypto functions and other pci bus agents * 66 mhz speed pending chip characterization. general description the ADSP-2141L safenet dsp is a highly integrated embedded secur ity processor that incorporates a sophisticated, general purpose dsp, along with a number of high performance cryp- tographic function blocks, as well as pci, dma and serial eeprom interfaces. it is fabricated in 0.35 m cmos triple- layer metal technology and uses a 3.3 v power supply. it is available in a 208-lead mqfp package with a commercial (0 c to 70 c) temperature range. dsp core the dsp is a standard analog devices adsp-218x core with full adsp-2100 family compatibility. the adsp-218x core combines the base dsp components from the adsp-2100 family with the addition of two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. the external memory interface of the 218x core has been extended to support up to 64m-words addressing for both program and data memory. some core enhancements have been added in the ADSP-2141L, including on-chip security rom and interrupt functions. refer to the analog devices adsp-2183 data sheet for further information. safenet cgx libraryCsecure kernel the safenet cgx library is a crypto library embodied as firm- ware (a secure kernel) that is mask-programmed into rom within the dsp. this solution protects the library from tampering. the cgx library provides the application programming interface (api) to applications that require security services from the ADSP-2141L. those applications may be software executing in user mode on the dsp, or they may be external host software accessing the ADSP-2141L via a pci bus. approximately 40 crypto commandscalled cgx (cryptographic extensions) are provided at the api and a simple control block structure is used to pass arguments into the secure kernel and return status. the cgx library includes integrated drivers for the various hardware crypto blocks on the chip. this allows the program- mer to ignore those details and concentrate on other product design issues. the cgx library firmware runs under a protected mode state of the dsp as described in the kernel mode control section following. this guarantees the security integrity of the sy stem during the execution of cgx processes and, for example, prevents disclosure of cryptographic key data or tampering with a secu rity operation. kernel mode control the kernel mode control subsystem is responsible for enforcing the security perimeter around the cryptographic functions of the ad sp-2141l. the device may operate in either user mode (kernel space is not accessible) or kernel mode (kernel space is accessible) at a given time. when in kernel mode, the kernel ram and certain protected crypto registers and functions (kernel space) are accessible only to the cgx library firmware. the cgx library executes host-requested macro-level functions and then returns control to the calling application. the kernel mode control subsystem resets the dsp should any security violation occur, such as attempting to access a protected memory location while in user mode.
rev. 0 ADSP-2141L C3C protected kernel ram the 4k 16 kernel ram provides a secure storage area on the ADSP-2141L for sensitive data such as keys or intermediate calculations during public key operations. the kernel mode control subsystem (above) enforces the protection by allowing only internal secure kernel mode access to this ram. a public keyset and a cache of up to 15 secret keys may be stored in kernel ram. secure key storage may be expanded to 700 secret keys by assigning segments of the dsps internal data ram to be protected. furthermore, a virtually unlimited number of data encryption keys may be stored in an encrypted form in off-chip memory. encrypt block the encrypt block performs high speed des and triple-des encrypt/decrypt operations. all four standard modes of des are supported: electronic code book (ecb), cipher block chaining (cbc), 64-bit output feedback (ofb) and 1-bit, 8-bit and 64- bit cipher feedback (cfb). the des encrypt/decrypt operations are highly pipelined and execute full 16-round des in only four clock cycles. hardware support for padding insertion, verification and removal further accelerates the encryption operation. con- text switching is provided to minimize the overhead of changing crypto keys and initialization vectors (ivs) to nearly zero. hash block the secure hash block is tightly coupled with the encrypt block and provides hardware accelerated one-way hash functions. both the md-5 and sha-1 algorithms are supported. combined operations that chain both hashing and encrypt/decrypt functions are provided in order to significantly reduce the processing time for data that needs both operations applied. for hash-then-encrypt and hash-then-decrypt operations, the ADSP-2141L can perform parallel execution of both functions from the same source and destination buffers. for encrypt-then-hash and decrypt-then-hash operations, the processing must be sequential, but minimum latency is still provided through the pipeline chaining design. an offset may be specified between the start of hashing and the start of encryption to support certain protocols such as ipsec. a mutable bit handler is also provided on the hash engine to facilitate ipsec ah processing. random number generator (rng) block the hardware random number generator provides a true, non- deterministic noise source for the purpose of generating keys, initialization vectors (ivs), and other random number require- ments. random numbers are provided as 16-bit words to the kernel. the cgx kernel requests random numbers as needed to perform requested cgx commands such as cgx_gen_key, and can also directly supply from 1 to 65,535 random bytes to a host application via the cgx_random command. public key accelerator the public key accelerator module works in concert with the cgx kernel firmware to provide full public key services to the host application. the kernel provides macro-level functions to perform diffie-hellman key agreement, rsa encrypt or decr ypt, dsa compute and verify digital signatures. the hardware accel- erator block speeds computation-intensive operations such as large vector multiply, add, subtract, square. pci/cardbus interface a full 40 mhz/33 mhz pci bus interface has been added to the core dsp functions. the 32-bit pci interface supports both bus master and target modes. the ADSP-2141L is capable of using dma to directly access data on other pci entities and pass that data through its encryption/hash engines. 32-bit dma controller the ADSP-2141L incorporates a high performance 32-bit dma controller which can be set up to move data efficiently between host pci memory, the hash/encrypt blocks, and/or external memory. the dma controller can be used with the pci bus in master mode, thus autonomously moving 32-bit data with mini- mal dsp intervention. up to 255 long words (1020 bytes) can be moved in a burst at up to 160 mbytes per second. application registers the application registers are a set of memory-mapped registers that facilitate communications between the ADSP-2141L and a host processor via the pci bus. one of the registers is a mailbox that is 44 bytes long and set up to hold the cgx command structure passed between the host and dsp processors. the application registers also provide the mechanism that allows the dsp and the external host to negotiate ownership of the hash/ encrypt block. serial eeprom interface the serial eeprom interface allows an external nonvolatile memory to be connected to the ADSP-2141L for storing pci configuration information (plug and play), as well as general- purpose nonvolatile storage. for example, encrypted (black) keys could be stored into eeprom for fast recovery after a power outage. interrupt controller the dsp core provides support for 14 interrupt sources, includ- ing six external and eight internal. all interrupts are prioritized into 12 levels and interrupt nesting may be enabled or disabled under software control. the security block interrupt controller provides enhancements to the dsp interrupt functions. primarily, the interrupt controller provides a new interrupt generation capability to the dsp or to an external host processor. under programmable configuration control, a crypto interrupt may be generated due to completion of certain operations such as encrypt complete, hash complete. the interrupt may either be directed at the dsp core (on irq2 ), or provided on an out- put line (pf7/ int_h ) to a host subsystem. laser variable storage the laser variable storage consists of 256 bits of tamper-proof factory-programmed data that is only accessible to the internal function blocks and the security kernel. included in these laser variable bits are: ? local storage variable (master key-encryption key) ? randomizer seed (to supplement the true entropy fed into the rng) ? program control data (enables/disables various features and configures the ADSP-2141L) ? crc of the laser data (to verify laser data integrity).
rev. 0 ADSP-2141L C4C the program control data bits (pcdbs) include configuration for permitted key lengths, algorithm enables, red kek loading. most of the pcdb settings may be overridden with a digitally signed token which may be loaded into the ADSP-2141L when it boots. these tokens are created by ire and each is targeted to a specific ADSP-2141L using a hash of its unique identity. downloadable secure code the ADSP-2141L allows additional security functions to be added to the device through a secure download feature. up to 16k words of code may be downloaded into internal memory within the dsp and this code can be given the security privileges of the cgx kernel firmware. all downloaded firmware is authenticated with a digital signature and verified with an on-chip public key. additional functions could include new encryption, hash or public key algorithms such as idea, rc-4, ripemd, elliptic curve, or any other application that needs direct control over the protected cryptographic hardware. 8k kernel top kernel mode (pmovlayl = c) (pmovlayh = 000) 8k kernel base kernel mode (pmovlayl = f) (pmovlayh = 000) 8k internal page (pmovlayl = 0) (pmovlayh = 000) 8k external page = 0 (pmovlayl = 1) (pmovlayh = 000) 8k external page 1 (pmovlayl = 2) (pmovlayh = 000) 8k kernel page 8191 (pmovlayl = 2) (pmovlayh = fff) 0x3fff 0x2000 8k internal (common bank) 0x1fff 0x0000 up to 64 megawords external program memory (pmovlayl alternates 2, 1, 2, 1...) pmovlayl = ls nibble of pmovlay pmovlayh = ms 3 nibbles of pmovlay shaded = kernel space figure 1. program memory (mmap = 0) 8k kernel top kernel mode (pmovlayl = c) (pmovlayh = 000) 8k internal (pmovlayl = 0) (pmovlayh = 000) 0x3fff 0x2000 0x1fff 0x0000 pmovlayl = ls nibble of pmovlay pmovlayh = ms 3 nibbles of pmovlay shaded = kernel space 8k kernel kernel mode (pmovlayl = d) (pmovlayh = 000) 8k kernel kernel mode (pmovlayl = e) (pmovlayh = 000) 8k kernel kernel mode (pmovlayl = f) (pmovlayh = 000) 8k external figure 2. program memory (mmap = 1) memory-mapped registers protected 4k kernel ram (dmovlay = 000f) kernel mode 8k internal (dmovlayl = 0) (dmovlayh = 000) 8k external page = 0 (dmovlayl = 1) (dmovlayh = 000) 8k external page 1 (dmovlayl = 2) (dmovlayh = 000) 0x2000 up to 64 megawords external data memory (dmovlayl alternates 2, 1, 2, 1...) shaded = kernel space 8k kernel page 8191 (dmovlayl = 2) (dmovlayh = fff) 32 memory-mapped registers 8160 words internal 0x1fff 0x1800 0x17ff 0x1000 0x0fff 0x0000 0x3fff 0x3fe0 0x3fdf figure 3. data memory architecture overview this section provides an architecture-level description of the unique function blocks within the ADSP-2141L. memory map the ADSP-2141L memory map is very similar to that of the adsp-2183 dsp, except that it includes significantly more off- chip memory addressing, and has additional crypto registers which are accessible to the user. dsp core the dsp core is architecturally identical to the adsp-218x with a few exceptions. ? the memory map includes additional external memory addressing through the pmovlay and dmovlay mecha- nisms. for more information, see the memory map section. ? additional memory-mapped crypto registers are available in the kernel data ram space. ? the pf7/ int_h flag pin may be reassigned to be the host interrupt output.
rev. 0 ADSP-2141L C5C ? irq2 now can include interrupt sources from the crypto subsystem, depending on interrupt mask registers. ? a new read register has been added to indicate the state of interrupt enable and interrupt masks. ? the kernel mode control subsystem has been added to super- vise the protected mode of operation of the dsp core. ? internal ram protection logic has been added to allow the kernel to seize increments of 1k word of internal pram and dram. ? bus mode configuration (218x vs. pci) pins have been added. ? 32k words of kernel program rom have been added to the dsp memory space. (see the memory map section.) kernel mode control the kernel mode control subsystem provides the following functions which serve to enforce the security integrity of the ADSP-2141L: ? provide a means to securely enter the kernel mode. ? provide a means to properly exit the kernel mode. ? prevent user mode access to protected memory and register locations. ? manage interrupts during kernel mode executions. ? manage the reset function to ensure that sensitive variables in dsp registers are erased. most of the kernel mode control functions are implemented in the hardware of the ADSP-2141L and are not directly visible to nonkernel applications (user mode). any attempt by a user mode application program running on the dsp to access a kernel space addresses (pram 0x2001 C 0x3fff, pmovlay 000c C 000f; or dram 0x0000 C 0x17ff, dmovlay 000f) results in an immediate chip reset and all sensitive registers and memory locations are erased. kernel mode may only be entered via a call, jump or increment to address 0x2000 with pmovlay set to 0x000f. once in kernel mode, any branch to nonkernel space program memory causes the dsp to return to user mode. (note: for security reasons when in kernel mode, the dsp does not respond to emulator bus requests.) the kernel mode can be interrupted during execution; however, during certain periods where sensitive data is being moved, all interrupts are disabled. within the interrupt service routine, another call to the kernel (cgx call) may be made if desired, although there are limitations on which cgx commands may preempt another. (for information, see the ADSP-2141L cgx interface programmers guide http://www.ire-ma.com/proddoc.htm.) only one level of kernel mode nesting is permitted. an interrupt to a user mode vector location while in nested kernel mode will also trigger the violation reset logic. once the interrupt service routine is finished, the return-from- interrupt must return control back to the kernel at the address/ overlay that was originally interrupted, otherwise the protection logic will issue a chip reset. hash and encrypt block overview the encrypt block is tightly coupled to the hash block in the ADSP-2141L and therefore the two are discussed together. refer to figure 4, hash/encrypt functional block diagram , for the following description. the algorithms implemented in the combined hash and encryp- tion block are: des, triple des, md-5 and sha-1. data can be transferred to and from the module once to perform both hashing and encryption on the same data stream. the des encrypt/decrypt operations are highly paralleled and pipelined, and execute full 16-round des in only four clock cycles. the internal data flow and buffering allows parallel execution of hashing and encryption where possible, and allows processing of data concurrently with i/o of previous and subsequent blocks. pad consume and verify write context hash digest read context rd dsp or pci 16-/32-bit output bus wr register address dsp or pci 16-/32-bit input bus encrypt/ decrypt block context storage (0/1) hash block pad insertion 512-bit fifo (encrypt-then-hash) (decrypt-then-hash) 7 512-bit fifo mutable bit processing pad insertion figure 4. hash/encrypt functional block diagram
rev. 0 ADSP-2141L C6C context switching is optimized to minimize the overhead of changing cryptographic keys to near zero. the software interface to the module consists of a set of memory-mapped registers, all of which are visible to the dsp and most of which can be enabled for host access via the pci bus. a set of five, 16-bit registers define the operation to be performed, the length of the data buffer to be processed, in bytes, the offset between the start of hashing and encryption (or vice versa), and the padding operation. if the data length is unknown at the time the encrypt/decrypt operation is started, the data length register may be set to zero, which specifies special handling. in this case, data may be passed to the hash/encrypt block indefinitely until the end of data is encountered. at that time, the operation is terminated by writing a new control word to the hash/encrypt control register (either to process the next packet or to invoke the idle state if there is no further work to do). this will close out the processing for the packet, including the addition of the selected crypto padding. a set of seven status registers provides information on when a new operation can be started, when there is space available to accept new data, when there is data available to be read out, and the results from the padding operation. crypto contexts there are two sets of crypto-context registers. each context contains a des or triple des key, initialization vector, and precomputed hashes (inner and outer) of the authentication key for hmac operations. the contexts also contain registers to reload the byte count from a previous operation (which is part of the hashing context), as well as an iv (also called salt ) for decrypting a black key, if necessary. once a crypto-context has been loaded and the operation defined, data is processed by writing it to a data input fifo. at the i/o interface, data is always written to, or read from, the same address. internally, the hash and encryption functions have separate 512-bit fifos, each with their own fifo man- agement pointers. incoming data is automatically routed to one or both of these fifos, depending on the operation in progress. output from the encryption block is read from the data output fifo. in encrypt-hash or decrypt-hash operations, the data is also automatically passed to the hashing data input fifo. output from the hash function is always read from the digest register of the appropriate crypto-context. the initialization vector to be used for a crypto operation can be loaded as part of a crypto-context. when an operation is complete, the same context will contain the resulting iv produced at the end, which can be saved away and restored later to continue the operation with more data. in certain packet-based applications such as ipsec, a feature is available that avoids the need for the control software to generate and load random ivs for outgoing (encrypted) packets. effec- tively, the iv register can be configured to be automatically updated with new random numbers for each encrypted packet, with almost no software intervention. padding when the input data is not a multiple of eight bytes (a 64-bit des block), the encrypt module can be configured to automati- cally append pad bytes. there are several options for how the padding is constructed, which are specified using the pad control word of the operation description. options include zero padding, pad-length character padding (pkcs#7), incrementing count, with trailing pad length and next header byte (for ipsec), or fixed character padding. note that for the ipsec and pkcs#7 pad protocols, there are cases where the padding not only fills out the last 8-byte block, but also causes an additional 8-byte block of padding to be added. for the hash operations, padding is automatically added as specified in the md-5 and sha-1 standards. when the hash final command is issued indicating the last of the input data, the algorithm-specified padding and data count bits are added to the end of the hash input buffer prior to computing the hash. data offsets certain security protocols, including ipsec, require portions of a data packet to be hashed while the remainder of the data is both hashed and encrypted. the ADSP-2141L supports this require- ment through the offset register, which allows specifying the number of 32-bit dwords of offset between the hash and encrypt/ decrypt operations. black key loads the cryptographic keys loaded as part of a crypto-context can be stored off-chip in a black , or encrypted, form. if the appropri- ate control bit is set (hecntl bit 15), the des or 3-des key will be decrypted immediately after it is written into the context register. the hardware handles this decryption automatically. the key encryption key (kek) that covers the black keys is loaded in a dedicated write-only kek register within the ADSP-2141L. the iv for decrypting the black secret key is called salt and must be stored along with the black key (as part of the context). note that 3-des cbc mode is used for pro- tecting 3- des black keys and single des cbc is used for single des black keys. when black keys are used, the key-decrypt operation adds a 6-cycle overhead (0.15 m s @ 40 mhz) for des keys or 36-cycle overhead (0.9 m s @ 40 mhz) for triple des keys each time a new crypto-context is loaded. (note that if the same context is used for more than one packet operation, the key decryption does not need to be performed again.) depending on the sequencing of operations, this key decryption may in fact be hidden (from a performance impact perspective) if other operations are underway. this is because the black key decryption process only requires that the des hardware be available. for example, if the dsp is reading the previous hash result from the output fifo, the black key decryption can be going on in parallel. also note that the data driver firmware does not have to wait for the key to be decrypted before writing data to the input fifo. the hard- ware automatically waits for the key to be decrypted before beginning to process data for a given packet. so, with efficient pipeline programming, it is possible to make the impact of black key essentially zero. the kek for key decryption is loaded via the secure kernel firmware using one of the cgx key manipulation commands. (for more information, see the command summary section.) this kek is typically the same for all black keys, since it is usually protecting local storage only. it is designated the dkek in the cgx api. one of the laser-programmed configuration bits specifies whether red (plaintext) keys are allowed to be loaded into the adsp- 2141l from a host. if the allowredkeyload laser bit is not set, keys may only be loaded in their black form. this is useful in systems where export restrictions limit the key length that may be used or where the external storage environment is untrusted.
rev. 0 ADSP-2141L C7C if the allowredkeyload bit is set, keys may be loaded either in their black form, or in the red or unencrypted form. note that the laser configuration bit may be overridden with a signed enabler token. (for more information, see the laser variable storage section.) depending on the definition of the security module boundary in a given application, fips 140-1 may require the use of black keys to protect key material. in other words, if the security boundary does not enclose the database where keys are stored, those keys must be protected from compromise. black key is a satisfactory way to meet this fips requirement. random number generator (rng) block the random number generator is designed to provide highly random, nondeterministic binary numbers at a high delivery rate with little software intervention. the random numbers are acces- sible to the kernel firmware in a 16-bit register that may be read by the dsp in kernel mode. once the register is read, the rng immediately generates a new 16-bit value that is available within 12 microseconds. all application-level access to random numbers should occur through the kernels cgx_random command (see the command summary section). the random number generator is designed using a shot noise true entropy source which is sampled by the master 40 mhz clock of the ADSP-2141L. the entropy source then feeds a complex nonlinear combinatorial circuit that produces the final rng output based on the interaction of the entropy source and the 40 mhz system clock. over 200 stages of linear feedback shift register (lfsr) are incorporated into the rng design. in order to facilitate fips 140-1 compliance, an option may be selected during cgx kernel initialization to enable an ansi x9.17 annex c post-randomizer to be applied to the output of the rng. this randomizer applies the des ecb algorithm multiple times to further disperse and whiten the random source. although this is not necessary to ensure the quality of the random numbers, it meets the criteria for a nist-approved random num- ber generation algorithm. public key accelerator (pkac) the public key arithmetic coprocessor (otherwise known as a bignum processor) is designed to support long vector calcula- tions of the kind needed to perform rsa, diffie-hellman and elliptic curve operations. the pkac can perform multiplication, squaring, addition and subtraction on arbitrary length bit vectors. the cgx software is responsible for setting the address register for the operands and result, as well as specifying the length and operation type. once the operation type field is written, the processor polls the opera- tion complete status while the calculation is carried out. the pkac utilizes the protected kernel ram for input, output and intermediate variable storage. it may only be accessed from the secure kernel mode. since public key computations typically take many milliseconds to complete, they may be preempted using a dsp interrupt. most application interaction with the public key accelerator will occur via the cgx software interface (see the command inter- face section). both high level public key operations such as rsa sign or create diffie-hellman key, as well as primitive operations such as multiply vector, add long vector, etc., are presented via the cgx interface. pci/cardbus interface the ADSP-2141L appears as a target on the pci bus as a single contiguous memory space of 128k bytes. in this memory space, the host can access the following: ? the unprotected internal crypto registers of the ADSP-2141L ? idma access to the dsps internal program memory (pm) and data memory (dm) ? paged access to external memory connected to the ADSP-2141L ? the kernel ram (kram) if it has been unprotected by an extended mode program as a pci master, the ADSP-2141L can transfer data between: ? the unprotected internal crypto registers and fifos of the ADSP-2141L and pci host memory ? external memory and pci host memory a 32-bit dma engine within the ADSP-2141L facilitates these transfers and permits full pci bandwidth use. serial eeprom interface the serial eeprom interface allows the ADSP-2141L to auto- matically read the pci configuration parameters at chip power-up. ire can provide the data content for the eeprom to properly set the chip device vendor id, type and properties for full com- pliance with the pci plug and play standards. in addition to being used for storage of host bus parameters, any extra space in the eeprom may be accessed by the dsp, either in user mode or kernel mode. support for this function is not included in the standard cgx command set. refer to the adsp-2141 u sers manual for the information on the data contents of the eeprom. refer to http://www.analog.com/ industry/dsp/ire.html. table i. interrupt sources internal interrupt sources external interrupt sources interrupt notes interrupt notes reset or power-up (pucr = 1) irq2 edge- or level-sensitive power-down irql1 level-sensitive sport0 transmit irql0 level-sensitive sport0 receive irqe edge-sensitive bdma interrupt irq1 edge- or level-sensitive sport1 transmit mixed with irq1 irq0 edge- or level-sensitive sport1 receive mixed with irq0 timer
rev. 0 ADSP-2141L C8C interrupt controller the dsp core of the ADSP-2141L provides a powerful set of interrupt sources. a total of 14 interrupt sources are available, although two pairs are multiplexed, yielding 12 simultaneous sources. refer to table i. the ADSP-2141L enhances the existing interrupt controller within the adsp-218x dsp core with some additional func- tions related to the crypto functional blocks and the external host bus interfaces. two additional interrupt controller sub- systems have been added to the basic interrupt controller as shown in figure 5. the dsp interrupt controller allows programming between one and nine sources for the irq2 interrupt to the dsp. the dimask register provides the mask to select which interrupt source is enabled. a pair of status registers, dumstat and dmstat, allow the dsp firmware to read the status of any interrupt source either before or after the mask is applied. the host interrupt controller allows programming between one and five sources for the pf7/ int_h interrupt output signal (which may be connected to the interrupt input of the host system). the hmask register provides the mask to select which interrupt source is enabled. a pair of status registers, humstat and hmstat, allow the host firmware to read the status of any interrupt source either before or after the mask is applied. laser variable storage the laser variables are configured through 256 fuses in the ADSP-2141L, which are programmed during ic manufacture. each ADSP-2141L produced is programmed with a unique set of laser variables. ? local storage variable (lsvthe master key-encrypt ion-key) ? internal seed variable h/e context0 done diclr difrc dimask host interrupt h/e context1 done host wrote cmd dma xfer done dma xfer queued ext mem conflict irq2 dicfg dsp interrupt controller dsp interrupt inth to host crypto interrupt subsystem boundry host unmasked status register dsp wrote cmd hash/enc error hash/enc error hiclr hifrc himask hicfg host interrupt controller ifc irq2 adsp-2183 interrupt controller imask icntl reset power down sport0 tx sport0 rx bdma int timer int sport1 tx sport1 rx internal interrupts irqe irql0 irql1 irq0 irq1 irq2 external interrupts dsp dsp masked status register dsp unmasked status register host masked status register h/e context1 done h/e context0 done figure 5. interrupt controller block diagram ? 48-bit program control data (enables/disables various fea- tures and configures the ADSP-2141L) ? crc of the laser data (to verify integrity of the laser bits) the lsv is a unique triple des mas ter key-encrypting key that allows the ADSP-2141L to securely store data (primarily other k eys) off-chip for later reloading. this is necessary if more storage space is needed than is available with on-chip ram, or if keys need to be saved and restored after a power outage. each ADSP-2141L produced is programmed with a unique, randomly generated local storage variable. the internal seed variable is used to randomly initialize the rng circuits before the entropy is mixed in. each ADSP-2141L produced is programmed with a unique, randomly generated internal seed variable which is loaded into the rng at chip boot time and cannot ever be read by software. the 48 program control data bits (pcdbs) include configura- tion for permitted key lengths, algorithm enables, red kek loading, internal ic pulse timing characteristics. the pcdbs provide configuration data that falls into three categories: ? internal ic pulse-timing characteristics ? ADSP-2141L hardware version number field ? ADSP-2141L feature enables the first two categories consist of data that cannot be altered once the ADSP-2141L has been fabricated. the feature enables can be overridden using a factory token enabler which may be passed to the cgx kernel as part of the cgx_init command. this token is digitally signed with an ire private key and verified internal to the ADSP-2141L with its public key. the cgx_init command is documented in the adsp-2141 cgx interface programmers guide (available from http://www.ire-ma.com/proddoc.htm).
rev. 0 ADSP-2141L C9C pin functions i/o descriptions this section describes the physical i/o hardware on the ADSP-2141L. pin function descriptionsCi/o hardware # of input/ pin name pins output function external memory bus address [25:0] 26 o address output pins for program, data, byte and i/o spaces (13 bits 2183, 13 bits from overlay register) note: a0 not used for 32-bit memory. data [31:0] 32 i/o data i/o pins for program and data memory spaces d31:0 are used for wide-bus data memory. d23:0 are used for dsp program ram. d23:8 are used for i/o space. d23:8 are used for dsp data ram. d15:8 are used for byte memory. d23:16 are also used as byte space addresses interrupts irq2 1 i edge- or level-sensitive interrupt request irql0 1 i level-sensitive interrupt requests irql1 1 i level-sensitive interrupt requests irqe 1 i edge-sensitive interrupt request bus signals br 1 i bus request input bg 1 o bus grant output bgh 1 o bus grant hung output pms 1 o program memory select output dmsl 1 o data memory select output (lower 16 bits for 32-bit dm) dmsh 1 o upper memory select output (upper 16 bits for 32-bit dm, not used for 16-bit dm) bms 1 o byte memory select output ioms 1 o i/o space memory select output cms 1 o combined memory select output ( pms , dms *, ioms , bms ) rd 1 o memory read enable output wr 1 o memory write enable output miscellaneous mmap 1 i memory map select input (1 = overlay external at 0x0000) bmode 1 i boot option control input (0 = bdma, 1 = idma) clkin, xtal 2 i clock or quartz crystal input (1/2 of the adsp-2141 clock) clkout 1 o processor clock output serial ports sport0 sclk0 1 i/o serial port 0 clock dr0 1 i serial port 0 receive data input rfs0 1 i/o serial port 0 receive frame sync dt0 1 o serial port 0 transmit data output tfs0 1 i/o serial port 0 transmit frame sync sport1 port configuration (system control reg) C> 1 = serial port 0 = other sclk1 1 i/o serial port 1 clock dr1 1 i serial port 1 receive data input flag in rfs1 1 i/o serial port 1 receive frame sync irq0 dt1 1 o serial port 1 transmit data output flag out tfs1 1 i/o serial port 1 transmit frame sync irq1 power-down pwd 1 i power-down initiate control pwdack 1 o power-down acknowledge
rev. 0 ADSP-2141L C10C # of input/ pin name pins output function flags pf6:0 7 i/o programmable i/o pins pf7/ int_h 1 i/o programmable i/o pinCorCinterrupt output (host mode) emulator ee 1 (emulator only) ebr 1 (emulator only) ebg 1 (emulator only) ereset 1 (emulator only) ems 1 (emulator only) eint 1 (emulator only) eclk 1 (emulator only) elin 1 (emulator only) elout 1 (emulator only) serial eeprom interface ee_di 1 o serial eeprom data in ee_do 1 i serial eeprom data out ee_cs 1 o serial eeprom chip select ee_sk 1 o serial eeprom clock bus select bus_mode 1 i processor bus select bus_sel 1 i bus select pci bus (dedicated pins) pci_clk 1 i pci clock pci_par 1 i/o pci parity bit pci_irdy 1 i/o pci initiator ready pci_stop 1 i/o pci abort transfer *when dms is enabled for generation of cms , the cms is activated for dsp access to external memory only, not for dma controller accesses. bus mode descriptions the pin function descriptions, bus mode table, shows the multiplexed pins in 2183 and pci mode. for more information on the pci pins mplx1Cmplx12, see the pin functions descriptionCpci mode multiplex bus table on the following page. pin function descriptionsbus mode # of input/ 2183 mode pci mode bus mode pins output (bus_mode = 0, bus_sel = 0) (bus_mode = 1, bus_sel = 0) mplx_reset 1 i reset_1 pci_ rst mplx1 1 i/o pci_ cbe3 mplx2 1 i/o pci_ cbe2 mplx3 1 i/o pci_ cbe1 mplx4 1 i/o pci_ cbe0 mplx5 1 i ird pci_idsel mplx6 1 i iwr pci_ gnt mplx7 1 i/o is pci_ frame mplx8 1 i/o ial pci_ devsel mplx9 1 i/o iack pci_ trdy mplx10 1 i/o fl0 pci_ perr mplx11 1 i/o fl1 pci_ serr mplx12 1 o fl2 pci_ req mplx_bus[31:0] 32 i/o iad15:0 pci_ad15:0 n/c 31:16 pci_ad31:16 power gnd 24 C ground pins vdd 22 C power supply pins (3.3 v) total: 208 includes the pins from this table and the i/o hardware pin function description table.
rev. 0 ADSP-2141L C11C idma mode multiplex bus pin definition idma port (218x mode) pin function descriptionsidma mode multiplex bus pin name idma name pins i/o description mplx5 ird 1 i idma port read input mplx6 iwr 1 i idma port write input mplx7 is 1 i idma port select mplx8 ial 1 i idma port address latch mplx9 iack 1 o idma port access ready acknowledge mplx10 fl0 1 o output flags mplx11 fl1 1 o output flags mplx12 fl2 1 o output flags mplx_bus iad 16 i/o idma data i/o pci port pin function descriptionspci mode multiplex bus pin name pci name pins i/o description mplx1 pci_ cbe3 1 i/o bus command / byte enable 3 mplx2 pci_ cbe2 1 i/o bus command / byte enable 2 mplx3 pci_ cbe1 1 i/o bus command / byte enable 1 mplx4 pci_ cbe0 1 i/o bus command / byte enable 0 mplx5 pci_idsel 1 i initialization device select mplx6 pci_ gnt 1 i bus grant mplx7 pci_ frame 1 i/o cycle frame mplx8 pci_ devsel 1 i/o device select mplx9 pci_ trdy 1 i/o target ready mplx10 pci_ perr 1 i/o parity error mplx11 pci_ serr 1 i/o system error mplx12 pci_ req 1 o pci bus request mplx_bus pci_ad15:0 pci_ad31:16 32 i/o pci address/data bus pf7/ int_h pci_ inta 1 o pci interrupt a request system interface the ADSP-2141L may be integrated into a wide variety of sys- tems, including those that already have a microprocessor and those that will use the ADSP-2141L as the main processor. the device can be configured into one of two host bus modes: idma or pci. idma bus mode the idma bus mode operates the same as in a native adsp- 218x device, as described in this section. the idma port provides an efficient means of communication between a host system and the ADSP-2141L. the port is used to access the on-chip program memory and data memory of the dsp with only one dsp cycle per word overhead. the idma port cannot, however, be used to write to the dsps memory- mapped control registers. the idma port has a 16-bit multiplexed address and data bus, and supports reading or writing 16-bit data (dm) or 24-bit program memory (pm). the idma port is completely asyn- chronous and can be written to while the ADSP-2141L is oper- ating at full speed. the dsp memory address is latched and then automatically incremented after each idma transaction. an external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. this increases throughput as the address does not have to be sent for each memory access. the idma port access occurs in two phases. the first is the idma address latch cycle. when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location; the destination type specifies whether it is a dm or pm access. the falling edge of the address latch signal latches this value to the idmaa register. once the address is stored, data can either be read from or written to the ADSP-2141Ls on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the ADSP-2141L that a particular transaction is required. in either case, there is a one-processor- cycle delay for synchronization. the memory access consumes an additional processor cycle. once an access has occurred, the latched address is automati- cally incremented and another access can occur. through the idmaa register, the ADSP-2141L can also specify the starting address and data format for dma operation. figure 6 illustrates a typical system configuration for the idma mode.
rev. 0 ADSP-2141L C12C adsp-2141 serial device 1/2x clock or crystal sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 serial device ird iwr is ial iack iad15C0 idma port 16 system interface or m controller irq2 irqe irql0 irql1 interrupt sources clkout clkin xtal fl0C2 pf0C7 mplx31C16 reset pci_clk pci_par pci_ irdy pci_ stop 16 nc nc pms cms (optional) dmsh dmsl addr25C0 26 a13C0 d23C16 32 d15C8 bms data 31C0 a10C0 d23C8 addr data cs 16-bit i/o space 2048 locations a0-a21 data cs byte memory (boot loader) ioms a25C0 d23C0 addr data 8192 8k 3 24 pm segments external memory bus program overlay memory a25C0* data overlay memory d15C0 8192 8k 3 16 segments d31C16 br bg bgh pwd pwdack up to 32m 3 32 bus arbiter bus_mode bus_sel vdd mmap bmode vdd or gnd ee_di ee_do ee_cs ee_sk eeprom nc *addr0 from the adsp-2141 is no connect for 32-bit memory. adsp-2141 addr1 is wired to ram a0. figure 6. ADSP-2141L idma system configuration
rev. 0 ADSP-2141L C13C adsp-2141 serial device 1/2x clock or crystal sclk1 rfs1 or irq0 tfs1 or irq1 dt1 or fo dr1 or fi sport1 sclk0 rfs0 tfs0 dt0 dr0 sport0 serial device pci_cbe3-0 pci_idsel pci_req pci_gnt pci_frame pci_devsel pci_trdy pci_perr pci_serr pci_ad31C0 pci_rst pci_clk pci_par pci_irdy pci_stop pf7/ int_h pci port 4 pci bus irq2 irqe irql0 irql1 interrupt sources clkout clkin xtal pf0C6 pms cms (optional) dmsh dmsl addr25-0 26 a13C0 d23C16 32 d15C8 bms data 31-0 a10C0 d23C8 addr data cs 16-bit i/o space 2048 locations a0-a21 data cs byte memory (boot loader) ioms a25C0 d23C0 addr data 8192 8k 3 24 pm segments external memory bus program overlay memory a25C0* data overlay memory d15C0 8192 8k 3 16 segments d31C16 br bg bgh pwd pwdack up to 32m 3 32 bus arbiter bus_mode bus_sel vdd mmap bmode vdd or gnd ee_di ee_do ee_cs ee_sk eeprom *addr0 from the adsp-2141 is no connect for 32-bit memory. adsp-2141 addr1 is wired to ram a0. 32 inta serial eeprom figure 7. ADSP-2141L pci system configuration pci bus mode figure 7 illustrates a typical system configuration for the pci mode.
rev. 0 ADSP-2141L C14C device operation operational modes security modes the ADSP-2141L operates in one of two security modes: kernel mode or user mode. the mode switching is performed on the fly as program execution proceeds. kernel mode is entered via a jump or call to address 0x2000 with pmovlay set to 0x000f. kernel mode will exit on its own once it has completed a requested operation (or terminates due to an error). special interrupt handling is performed if the dsp is executing in kernel mode. while executing a cgx command in kernel mode, it is possible to interrupt to a nonprotected vector loca- tion and then invoke the kernel again during the interrupt han- dler. the [if condition] rti instruction must be used to return to the kernel from the interrupt handler. the return address and pmovlay page must match the interrupted ad- dress and pmovlay page. if not, the violation reset logic will be triggered. only one level of kernel mode nesting is permitted. an interrupt to a nonprotected vector location while in nested kernel mode will also trigger the violation reset logic. while in kernel mode, it is possible to interrupt to a protected vector location. in this case, the processor remains in kernel mode. the [if condition] rti instruction must be used to return the processor from the interrupt handler. there is no imposed limit on the number of nested interrupts to a protected vector location. bus modes the ADSP-2141L host bus may be configured for one of two personalities: idma mode or pci bus mode. the selection of mode is made with two hardware control inputs bus_mode and bus_sel at boot time. table ii. bus mode selection bus mode pins bus_mode bus_sel idma mode 0 0 pci bus mode 1 0 this selection may not be changed after the ADSP-2141L comes out of power-up reset. it is typically expected that the bus mode signals are tied to ground or vdd on the pc board. boot modes the ADSP-2141L may be bootstrap-loaded from one of three sources: byte-wide memory, host processor bus, or external program memory. the selection of mode is made with two hardware control inputs bmode and mmap. when the host processor boot mode is selected, any one of the two bus modes may be used. table iii. boot mode selection boot mode pins bmode mmap byte-wide (bdma) boot mode 0 0 host bus (idma) boot mode 1 0 external program boot mode 0 1 the hardware pin states are not relevant after the ADSP-2141L comes out of power-up reset. refer to the ADSP-2141L users manual (available from ire) for information on bdma, idma and external program boot modes. command interface this section provides a general overview of the software com- mand interface to the crypto functions in the ADSP-2141L. refer to the adsp-2141 cgx interface programmers guide (available from http://www.ire-ma.com/proddoc.htm) for more details. overview the ADSP-2141L provides an embedded crypto library that provides a command interface api (application programming interface) to outside applications. these commands are referred to as cgx (cryptographic extensions). the cgx api simultaneously enforces certain security policies within the ADSP-2141L and insulates applications from the details of many complex cryptographic operations. the security policy built into the ADSP-2141L has some of the following rules: ? unencrypted (red) keys may never be retrieved from the ADSP-2141L. ? keys within the ADSP-2141L are marked with an attributes field that specifies key type and trust level. ? a keys type field must match the use in a requested opera- tion (i.e., cannot use a kek to encrypt traffic). ? keys generated internal to the ADSP-2141L (i.e., from rng) are marked as trusted. ? keys that are negotiated or imported from outside systems are marked untrusted (although they may still be quite secure). ? separate trusted and untrusted key hierarchies may be main- tained and customer applications may choose which trust level is required for a given command. for most key management operations, the cgx interface must be used. however, for certain high performance encryption/ hashing applications, the cgx interface may be bypassed and either the dsp or a host processor may exercise direct control over the hash/encrypt block.
rev. 0 ADSP-2141L C15C command summary approximately 40 cgx commands are supported in the api to the ADSP-2141L. general utilities init initializes secure kernel and allow reconfiguration of the ADSP-2141L default restores factory default settings random generates random numbers (between 1k and 64k bytes) get chipinfo returns ADSP-2141L system information self test runs a suite of self-tests on the hardware and cgx symmetrical key management uncover key loads and decrypts a secret key gen key generates a secret key gen kek generates an internal key encryption key gen rkek generates a key recovery key encryption key save key saves a key protected by the recovery key (rkek) load key imports a red (plaintext) user secret key derive key derives a secret key from a pass phrase transform key transforms a secret key using ipsec destroy key removes secret key from the kcr export key exports an ire-format secret key import key imports an ire-format secret key symmetrical encryption encrypt encrypts data decrypt decrypts data load kg loads secret key into hw/sw key generator hash hash init initializes the hash operator hash data hash customer data hash encrypt hash and encrypt customer data hash decrypt hash and decrypt customer data prf functions merge key combines two secret keys into one key merge long key combines two secret keys into a data string (long key) extract long key creates a secret key from a data string (long key) prf data hash multiple data items using hmac prf key completes the above hmac and create secret key asymmetrical key management gen pubkey generates a public keyset (public and private parts) gen newpubkey generates a part of a public keyset gen negkey generates a diffie-hellman derived secret key export pubkey exports an ire-format public key import pubkey imports an ire-format public key asymmetrical encryption pubkey encrypt encrypts data using rsa public key pubkey decrypt decrypts data using rsa public key digital signatures sign digitally signs a message verify verifies a digital signature math utilities add vector performs a vector add operation sub vector performs a vector subtract operation mult vector performs a vector multiply operation exp vector performs a vector exponentiate operation shift vector performs a vector right or left shift operation extended mode load extended loads/enables extended (downloaded) algorithm block execute extended executes extended (downloaded) algorithm block
rev. 0 ADSP-2141L C16C absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +4.6 v input voltage . . . . . . . . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v output voltage swing . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v operating temperature range (ambient) . . . . . 0 c to 70 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (5 sec) mqfp . . . . . . . . . . . . . . . . . 280 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADSP-2141L features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device frequency dependency for timing specifications t ck is defined as 0.5t cki . the ADSP-2141L uses an input clock with a frequency equal to half the instruction rate: a 20.0 mhz input clock (which is equival ent to 50 ns) yields a 25 ns processor cycle ( equivalent to 40 mhz). t ck values within the r ange of 0.5t cki period should be substituted for all relevant timing parameters to obtain the specification value. example: t ckh = 0.5t ck C 7 ns = 0.5 (25 ns ) C 7 ns = 8 ns
rev. 0 C17C recommended operating conditions k grade parameter min max unit v dd supply voltage 3.0 3.6 v t amb ambient operating temperature 0 70 c electrical characteristics dc specifications k grade parameter test conditions min typ max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin/reset voltage @ v dd = max 2.4 v v il lo-level input voltage 1, 3 @ v dd = min 0.4 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 m a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 v i ih hi-level input current 3 @ v dd = max v in = v dd max 10 m a i il lo-level input current 3 3 @ v dd = max v in = 0 v 10 m a i ozh three-state leakage current 7 @ v dd = max v in = v dd max 8 10 m a i ozl three-state leakage current 9 @ v dd = max v in = 0 v 9 8 m a i dd supply current (idle) 10, 11 @ v dd = 3.3 t amb = 25 c t ck = 25 ns 12 16 ma t ck = 30 ns 12 15 ma i dd supply current (dynamic) 11, 13 @ v dd = 3.3 t amb = 25 c t ck = 25 ns 12 195 ma t ck = 30 ns 12 165 ma c i input pin capacitance 3, 6, 14 @ v in = 2.5 v f in = 1.0 mhz t amb = 25 c8pf c o output pin capacitance 6, 7, 14, 15 @ v in = 2.5 v f in = 1.0 mhz t amb = 25 c8pf notes 1 bidirectional pins: d0Cd31, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, iad0C15, pf0Cpf7. 2 input only pins: irq2 , br , mmap, bmode, bus mode, bus sel, dr0, dr1, pwd , irql0 , irql1 , irqe , is , ird , iwr , ial. 3 input only pins: clkin, reset , irq2 , br , mmap, bmode, bus mode, bus sel, dr0, dr1, pwd , irql0 , irql1 , irqe , is , ird , iwr , ial. 4 output pins: bg , bgh , pms , dmsl , dmsh , bms , ioms , cms , rd , wr , iack , pwdack, a0Ca25, dt0, dt1, clkout, fl2C0. 5 although specified for ttl outputs, all ADSP-2141L outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 output pins: bg , bgh , pms , dmsl , bms , ioms , dmsh , cms , rd , wr , iack , pwdack, a0Ca25, dt0, dt1, clkout, fl2C0, ee_di, ee_cs, ee_sk. 8 0 v on br. clkin active (to force three-state condition). 9 three-statable pins: a0Ca25, d0Cd31, pms , dmsl , dmsh , bms , ioms , cms , rd , wr , dt0, dt1, sckl0, sclk1, tfs0, tfs1, rfs0, rfs1, iad0C iad15, pf0Cpf7. 10 idle refers to ADSP-2141L state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 11 current reflects device operating with no output loads. 12 v in = 0.4 v and 2.4 v. for typical supply currents, refer to power dissipation section. 13 i dd measurement taken with 93% of instructions executing from internal memory and 7% from external memory. h/e operations are exec uting from internal memory concurrently with pci transactions. initialization operations are executed from external memory. 14 applies to mqfp package type. 15 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. ADSP-2141L specifications
rev. 0 ADSP-2141L C18C dc specificationsC pci bus pins k grade parameter test conditions min max unit v ih hi-level input voltage 1, 2 0.5 v dd v dd + 0.5 v v il lo-level input voltage 1, 2 C0.5 0.3 v dd v v oh hi-level output voltage 1, 3 i out = C500 m a 0.9 v dd v v ol lo-level output voltage 1, 3 i out = 1500 m a 0.1 v dd v i ih hi-level input current 2 0 < v in < v dd 10 m a i il lo-level input current 2 0 < v in < v dd 10 m a i ozh three-state leakage current 4 0 < v in < v dd 10 m a i ozl three-state leakage current 1 0 < v in < v dd 10 m a c i input pin capacitance t amb = 25 c10pf c clk pci clk pin capacitance t amb = 25 c5 12pf c idsel pci idsel pin capacitance 5 t amb = 25 c8pf l pin pin inductance 20 nh notes 1 bidirectional pins: mplx_bus [31:0}, mplx1C4, mplx7C10, mplx12 2 input only pins: mplx_reset, mplx5, mplx6, pci_clk, pci_par, pci_irdy, pci_stop 3 output only pins: mplx11 4 leakage currents include high-z output leakage for bidirectional buffers with three-state outputs. 5 lower capacitance of idsel (mplx_5) input-only pin allows for nonresistive connection to address/data bus. timing parameters pci clock (guaranteed over operating temperature and digital supply range) the ADSP-2141L is targeted for use in pci add-on i/o slave card designs. it provides a glueless interface to the pci bus. all b us drivers are compliant with pci interface electrical switching and drive capability specifications. the ADSP-2141L does not implement the following signals: lock , intb , intc , intd , sbo , sdone , clkrun, ad[64:32], c/be [7:4], req 64, ack 64, par64. parameter min max unit timing requirements: t cyc clk cycle time 25 100 ns t high clk high time 11 ns t low clk low time 11 ns clk slew rate 1 1 4 v/ns rst slew rate 2 50 mv/ns notes 1 rise and fall times are specified in terms of the edge rate measured in v/ns. this slew rate must be met across the minimum pea k-to-peak portion of the waveform as shown in figure 8. 2 the minimum rst slew rate applies only to the rising (deassertion) edge of the reset signal, and ensures that system noise cannot render an ot herwise monotonic signal to appear to bounce in the switching range. 0.2v cc 2v p-p ( minimum ) 0.3v cc 0.4v cc 0.5v cc 0.6v cc t low t high t cyc figure 8. clock waveform
rev. 0 ADSP-2141L C19C parameter min max unit pci bus interface timing requirements: t val clk to signal valid 2 11 ns t on clk to low-z delay 2 ns t off clk to high-z delay 28 ns t su input setup to clk 7 ns t h input hold after clk 1 ns t rst-off rst active to outputs high-z 40 ns v step (3.3v signaling) v tl v test v th v test inputs valid output current # leakage current v test t val clk output delay t on t off three-state output t su t h v max v th v tl clk input figure 9. output (top) and input timing measurement conditions
rev. 0 ADSP-2141L C20C parameter min max unit clock signals and reset timing requirements: t cki clkin period 50 100 ns t ckil clkin width low 15 ns t ckih clkin width high 15 ns switching characteristics: t ckl clkout width low 0.5t ck C 7 ns t ckh clkout width high 0.5t ck C 7 ns t ckoh clkin high to clkout high 0 20 ns control signals timing requirement: t rsp reset width low 1 5t ck ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable c lkin (not including crystal oscillator start-up time). t ckih t cki t ckil t ckoh t ckh t ckl clkin clkout figure 10. clock signals and reset
rev. 0 ADSP-2141L C21C parameter min max unit interrupts and flags timing requirements: t ifs irqx , fi, or pfx setup before clkout low 1, 2, 3, 4 0.25t ck + 15 ns t ifh irqx , fi, or pfx hold after clkout high 1, 2, 3, 4 0.25t ck ns switching characteristics: t foh flag output hold after clkout low 5 0.5t ck C 7 ns t fod flag output delay from clkout low 5 0.5t ck + 5 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (refer to the interrupt controller operation section in the program control chapter of the adsp-2100 family users manual for further informa- tion on interrupt servicing.) 2 edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , irq2 , irql0 , irql1 , irqe . 4 pfx = pf0, pf1, pf2, pf3, pf4, pf5, pf6, pf7. 5 flag outputs = pfx, fl0, fl1, fl2, flag_out. t fod t foh t ifh t ifs clkout flag outputs irqx fi pfx figure 11. interrupts and flags
rev. 0 ADSP-2141L C22C parameter min max unit bus request/bus grant timing requirements: t bh br hold after clkout high 1 0.25t ck + 2 ns t bs br setup before clkout low 1 0.25t ck + 17 ns switching characteristics: t sd clkout high to xms , rd , wr disable 0.25t ck + 10 ns t sdb xms , rd , wr disable to bg low 0 ns t se bg high to xms , rd , wr enable 0 ns t sec xms , rd , wr enable to clkout high 0.25t ck C 6 ns t sdbh xms , rd , wr disable to bgh low 2 0ns t seh bgh high to xms , rd , wr enable 2 0ns notes xms = pms , dmsl , dmsh , cms , ioms , bms. 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise, the signal will be recogni zed on the following cycle. refer to the adsp-2100 family users manual for br / bg cycle relationships. 2 bgh is asserted when the bus is granted and the processor requires control of the bus to continue. t bh t bs t sd t sdb t sdbh clkout br clkout pms , dmsl , bms , rd , wr bg bgh t sec t se t seh figure 12. bus request/bus grant
rev. 0 ADSP-2141L C23C parameter min max unit external memory write: ADSP-2141L dma initiated switching characteristics: t a clock to address and dmsx 59ns t dw data setup before write deasserted 0.5t ck C 2 + w ns t dh data hold after write deasserted 0.5t ck C 8 ns t wp write pulsewidth 0.5t ck C 5 + w ns t wde write low to data enabled C5 ns t asw address, dmsx setup before write low 1 ns t ddr data disable before write/read low 0 ns t cwr clock high to write low 6 12 ns t aw address, dmsx setup before write high 0.5t ck C 2 + w ns t ah address and dmsx hold after clock 2 ns t wra address, dmsx hold after write high 0.5t ck C 7 ns t wwr write high to read/write low 0.5t ck C 3 ns 1. if wait-state(s) added, then referenced to last wait-state clock interval. 2. w = dma wait states t ck . t ah 25ns (ref @ 40mhz) t asw t a t aw t wra t wwr t cwr t wp t wde t dw t dh t ddr dsp clock out ext. addr (a25C0) ext. dmsh ext. dmsl ext. wr ext. data (d31C0) figure 13. external memory write: ADSP-2141L dma initiated
rev. 0 ADSP-2141L C24C parameter min max unit external memory readADSP-2141L dma initiated timing requirements: t rdd read low to data valid 0.5t ck C 8 + w ns t aa address, dmsx valid to data valid 0.5t ck C 3 + w ns t sur data valid before read deasserted 4 ns t rdh data hold after read deasserted 1 ns switching characteristics: t a clock to address and dmsx active 5 9 ns t asr address, dmsx setup before read low 2 ns t ah address and dmsx hold after clock 2 ns t rda address, dmsx hold after read high 0.5t ck C 7 ns t crd clock high to rd low 8 12 ns t rp read pulsewidth 0.5t ck C 5 + w ns t rwr rd high to read or write low 0.5t ck C 3 ns 1. if wait-state(s) added, then referenced to last wait-state clock interval. 2. w = dma wait states t ck . 25ns (ref @ 40mhz) t a t aa t rdd dsp clock out ext. addr (a25C0) ext. dmsh ext. dmsl ext. rd ext. data (d31C0) t ah t rda t asr t crd t rp t sur t rdh t rwr figure 14. external memory read C ADSP-2141L dma initiated
rev. 0 ADSP-2141L C25C parameter min max unit external memory write: ADSP-2141L dsp initiated switching characteristics: t a clock to address, xms 16ns t dw data setup before write deasserted 0.5t ck C 7 + w ns t dh data hold after write deasserted 0.25t ck C 3.5 ns t wp write pulsewidth 0.5t ck C 5 + w ns t wde write low to data enabled 0 ns t asw address, xms setup before write low 0.25t ck C 4 ns t ddr data disable before write/read low 0.25t ck C 4 ns t cwr clock high to write low 0.25t ck 0.5t ck + 9 ns t aw address, xms setup before write high 0.75t ck C 6 + w ns t ah address, xms hold after clock 1 ns t wra address, xms hold after write high 0.25t ck C 4 ns t wwr write high to read/write low 0.5t ck C 5 ns 1. if wait-state(s) added, then referenced to last wait-state clock interval. 2. w = dsp wait states t ck . t aw dsp clock out ext. addr (a13C0) ext. wr ext. data (d23C0) t ah t wra t asw t wp 25ns (ref @ 40mhz) t a t cwr t wwr t wde t dw t dh t ddr pms , dmsx , bms , ioms , cms figure 15. external memory write: ADSP-2141L dsp initiated
rev. 0 ADSP-2141L C26C parameter min max unit external memory readADSP-2141L dsp initiated timing requirements: t rdd read low to data valid 0.5t ck C 10 + w ns t aa address, xms valid to data valid 0.75t ck C 11.5 + w ns t sur data valid before read deasserted 9 ns t rdh data hold after read deasserted 0 ns switching characteristics: t a clock to address, xms active 1 6 ns t asr address, xms setup before read low 0.25t ck C 4 ns t ah address, xms hold after clock 1 ns t rda address, xms hold after read high 0.25t ck C 3 ns t crd clock high to rd low 0.25t ck C 2 0.25t ck + 7 ns t rp read pulsewidth 0.5t ck C 5 + w ns t rwr rd high to rd or wr low 0.5t ck C5 ns 1. if wait-state(s) added, then referenced to last wait-state clock interval. 2. w = dsp wait state t ck . dsp clock out ext. addr (a13C0) ext. rd ext. data (d23C0) t aa 25ns (ref @ 40mhz) t rda t crd t ah t asr pms , dmsx , bms , ioms , cms t a t rp t sur t rdd t rdh t rwr figure 16. external memory read C ADSP-2141L dsp initiated
rev. 0 ADSP-2141L C27C parameter min max unit serial ports timing requirements: t sck sclk period 50 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 7 ns t scp sclk in width 15 ns switching characteristics: t cc clkout high to sclkout 0.25t ck 0.25t ck + 10 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 15 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 15 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 14 ns t scdd sclk high to dt disable 15 ns t rdv rfs (multichannel, frame delay zero) to dt valid 15 ns clkout t cc t sch t cc t sck t scp t scp t scs t rd t rh t scdv t scdd t scdh t scde t tde t tdv t rdv t tde t tdv t rdv sclk dr tfs in rfs in rfs out tfs out dt tfs out alternate frame mode rfs out multichannel mode frame delay 0 (mfd = 0) tfs in alternate frame mode rfs in multichannel mode frame delay 0 (mfd = 0) figure 17. serial ports
rev. 0 ADSP-2141L C28C parameter min max unit idma address latch (idma mode multiplex bus) timing requirements: t ialp duration of address latch 1, 2 10 ns t iasu mplx_bus address setup before address latch end 2 5ns t iah mplx_bus address hold after address latch end 2 3ns t ika mplx9 low before start of address latch 2, 3 0ns t ials start of write or read after address latch end 2, 3 4ns notes 1 start of address latch = mplx7 low and mplx8 high. 2 start of write or read = mplx7 low and mplx6 low or mplx5 low. 3 end of address latch = mplx7 high or mplx8 low. t ika t ialp t iasu t iah t ials mplx9 / iack mplx8 / ial mplx7 / is mplx _bus / iad15C0 mplx5 or mplx6 / ird or iwr figure 18. idma address latch (idma mode multiplex bus)
rev. 0 ADSP-2141L C29C parameter min max unit idma write, short write cycle (idma mode, multiplex bus) timing requirements: t ikw mplx9 low before start of write 1 0ns t iwp duration of write 1, 2 15 ns t idsu mplx_bus data setup before end of write 2, 3, 4 5ns t idh mplx_bus hold after end of write 2, 3, 4 3ns switching characteristic: t ikhw start of write to mplx9 high 15 ns notes 1 start of write = mplx7 low and mplx6 low. 2 end of write = mplx7 high or mplx6 high. 3 if write pulse ends before mplx9 low, use specifications t idsu , t idh . 4 if write pulse ends after mplx9 low, use specifications t iksu , t ikh. data t ikw t ikhw mplx9 / iack mplx7 / is mplx _bus / iad15C0 t iwp t idh t idsu mplx6 / iwr figure 19. idma write, short write cycle (idma mode, multiplex bus)
rev. 0 ADSP-2141L C30C parameter min max unit idma write, long write cycle (idma mode, multiplex bus) timing requirements: t ikw mplx9 low before start of write 1 0ns t iksu mplx_bus data setup before mplx9 low 2, 3, 4 0.5t ck + 10 ns t ikh mplx_bus data hold after mplx9 low 2, 3, 4 2ns switching characteristics: t iklw start of write to mplx9 low 4 1.5t ck ns t ikhw start of write to mplx9 high 15 ns notes 1 start of write = mplx7 low and mplx6 low. 2 if write pulse ends before mplx9 low, use specifications t idsu , t idh. 3 if write pulse ends after mplx9 low, use specifications t iksu , t ikh. 4 this is the earliest time for mplx9 low from start of write. for idma write cycle relationships, please refer to the adsp-2100 family users manual . t ikw t iklw mplx9 / iack mplx7 / is mplx _bus / iad15C0 t ikhw t iksu t ikh data mplx6 / iwr figure 20. idma write, long write cycle (idma mode, multiplex bus)
rev. 0 ADSP-2141L C31C parameter min max unit idma read, long read cycle (idma mode, multiplex bus) timing requirements: t ikr mplx9 low before start of read 1 0ns t irp duration of read 1 15 ns switching characteristics: t ikhr mplx9 high after start of read 1 15 ns t ikds mplx_bus data setup before mplx9 low 0.5t ck C 7 ns t ikdh mplx_bus data hold after end of read 2 0ns t ikdd mplx_bus data disabled after end of read 2 14 ns t irde mplx_bus previous data enabled after start of read 0 ns t irdv mplx_bus previous data valid after start of read 15 ns t irdh1 mplx_bus previous data hold after start of read (dm/pm1) 3 2t ck C 5 ns t irdh2 mplx_bus previous data hold after start of read (pm2) 4 t ck C 5 ns notes 1 start of read = mplx7 low and mplx5 low. 2 end of read = mplx7 high or mplx5 high. 3 dm read or first half of pm read. 4 second half of pm read. t ikhr mplx9 / iack mplx7 / is mplx _bus / iad15C0 t ikr t irp t ikdh t ikds t irde previous data read data t irdv t ikdd t irdh mplx6 / ird figure 21. idma read, long read cycle (idma mode, multiplex bus)
rev. 0 ADSP-2141L C32C parameter min max unit idma read, short read cycle (idma mode, multiplex bus) timing requirements: t ikr mplx9 low before start of read 1 0ns t irp duration of read 15 ns switching characteristics: t ikhr mplx9 high after start of read 1 15 ns t ikdh mplx_bus data hold after end of read 2 0ns t ikdd mplx_bus data disabled after end of read 2 14 ns t irde mplx_bus previous data enabled after start of read 0 ns t irdv mplx_bus previous data valid after start of read 15 ns notes 1 start of read = mplx7 low and mplx5 low. 2 end of read = mplx7 high or mplx5 high. mplx_bus/iad15C0 mplx6/ ird mplx7/ is mplx9/ iack t ikr t ikhr t irp t irde t ikdh previous data t irdv t ikdd figure 22. idma read, short read cycle (idma mode, multiplex bus)
rev. 0 ADSP-2141L C33C capacitive loading figures 23 and 24 show the capacitive loading characteristics of the ADSP-2141L. c l C pf rise time (0.4v C 2.4v) C ns 0 50 18 14 t = +70 8 c v dd = 3.0v 16 12 10 8 6 4 2 0 100 150 200 250 300 figure 23. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) c l C pf 18 C2 0 250 50 100 150 200 16 10 6 2 nominal 14 12 8 4 C4 valid output delay or hold C ns figure 24. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the out- put disable time (t dis ) is the difference of t measured and t decay , as shown in the output enable/disable diagram. the time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 v from the measured output high or low voltage. the decay time, t decay , is dependent on the capacitive load, c l , and the current load, i l , on the output pin. it can be approximated by the fol- lowing equation: t decay = c l 0.5 v i l from which t dis = t measured t decay is calculated. if multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. 1.5v input or output 1.5v figure 25. voltage reference levels for ac measure- ments (except output enable/disable) output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram. if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) C 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 26. output enable/disable to output pin 50pf +1.5v i oh i ol figure 27. equivalent device loading for ac measure- ments (including all fixtures)
rev. 0 ADSP-2141L C34C table iv. thermal ratings: mqfp package rating description symbol value (mqfp still air) value (mqfp 9500 fpm) thermal resistance (case to ambient) q ca 30.7 c/w 16.7 c/w thermal resistance (junction to ambient) q ja 35 c/w 21 c/w thermal resistance (junction to case) q jc 4.3 c/w 4.3 c/w environmental conditions the following figures assume a four-layer jedec printed circuit board: t amb = t case C ( pd q ca ) t case = case temperature in c output drive currents figures 28 and 29 show typical i-v characteristics for the output drivers of the ADSP-2141L. the curves represent the current drive capability of the output drivers as a function of output voltage. source voltage C v 100 C40 C100 0 3.5 source current C ma 0.5 1.0 1.5 2.0 2.5 3.0 80 C20 C60 C80 40 0 60 20 v dd = 3.0v @ +70 8 c 4.0 v dd = 3.3v @ +25 8 c v dd = 3.6v @ 0 8 c v dd = 3.0v @ +70 8 c v dd = 3.3v @ +25 8 c v dd = 3.6v @ 0 8 c figure 28. typical drive currents (pci pins) source voltage C v C40 0 3.5 source current C ma 0.5 1.0 1.5 2.0 2.5 3.0 80 C20 C60 C80 40 0 60 20 v dd = 3.0v @ +70 8 c 4.0 v dd = 3.3v @ +25 8 c v dd = 3.6v @ 0 8 c v dd = 3.0v @ +70 8 c v dd = 3.3v @ +25 8 c v dd = 3.6v @ 0 8 c v oh v ol figure 29. typical drive currents (addr/dbus/rd/wr pins) power dissipation total power dissipation has two components: one due to inter- nal circuitry and one due to the switching of external output drivers. internal power dissipation depends on the sequence in which instructions execute and the data operands involved. see i ddin calculation in electrical characteristics section. internal power dissipation is calculated this way: p int = i ddin v dd the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: C the number of output pins that switch during each cycle (o) C the maximum frequency at which the pins can switch (f) C the load capacitance of the pins (c) C the voltage swing of the pins (v dd ). the external component is calculated using: p ext = o c v dd 2 f the load capacitance should include the processors package capacitance (c in ). the frequency f includes driving the load high and then back low.
rev. 0 ADSP-2141L C35C example: in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions: ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 3.3 v and t ck = 25 ns. total power dissipation = p int + (c v dd 2 f ) p int = internal power dissipation from power vs. frequency graphs (figures 30 and 31). ( c v dd 2 f ) is calculated for each output: # of pins c v dd 2 f address, dms 8 10 pf 3.3 2 v 40 mhz = 34.8 mw data output, wr 9 10 pf 3.3 2 v 20 mhz = 19.6 mw rd 1 10 pf 3.3 2 v 40 mhz = 2.2 mw clkout 1 10 pf 3.3 2 v 20 mhz = 4.4 mw 61.0 mw total power dissipation for this example is p int +61 mw. frequency C mhz 940 40 power (p int ) C mw 33 34 35 36 37 38 840 340 640 440 740 540 42 32 41 39 v dd = 3.6v v dd = 3.3v v dd = 3.0v 706mw 554mw 431mw 823mw 649mw 509mw power, internal figure 30. power vs. frequency frequency C mhz 80 40 power (p idle ) C mw 33 34 35 36 37 38 75 40 65 50 70 60 42 32 41 39 v dd = 3.6v v dd = 3.3v v dd = 3.0v 68mw 51mw 41mw 74mw 53mw 43mw 55 45 power, idle figure 31. power vs. frequency
rev. 0 ADSP-2141L C36C pin configurations for all multiplexed pins the active sense is determined by the mode selected. pin # pin name pin # pin name pin # pin name pin # pin name pin # pin name 1 ems 43 pci_clk 85 vdd 127 gnd 169 gnd 2 ee 44 gnd 86 gnd 128 addr[0] 170 data[0] 3 gnd 45 mplx_bus[30] 87 mplx6 129 addr[1] 171 data[1] 4 eclk 46 mplx_bus[29] 88 mplx5 130 addr[2] 172 data[2] 5 elout 47 mplx_bus[28] 89 mplx_bus[15] 131 addr[3] 173 data[3] 6 elin 48 mplx_bus[27] 90 mplx_bus[14] 132 vdd 174 vdd 7 eint 49 vdd 91 mplx_bus[13] 133 addr[4] 175 gnd 8 ebr 50 gnd 92 mplx_bus[12] 134 addr[5] 176 data[4] 9 ebg 51 mplx_bus[26] 93 vdd 135 addr[6] 177 data[5] 10 mmap 52 mplx_bus[25] 94 gnd 136 addr[7] 178 data[6] 11 bmode 53 mplx_bus[24] 95 mplx_bus[11] 137 addr[8] 179 data[7] 12 bus_mode 54 mplx1 96 mplx_bus[10] 138 addr[9] 180 data[8] 13 bus_sel 55 mplx_bus[23] 97 mplx_bus[9] 139 addr[10] 181 data[9] 14 ee_sk 56 mplx_bus[22] 98 mplx_bus[8] 140 addr[11] 182 data[10] 15 ee_cs 57 vdd 99 vdd 141 addr[12] 183 data[11] 16 ee_di 58 gnd 100 gnd 142 addr[13] 184 data[12] 17 ee_do 59 mplx_bus[21] 101 mplx4 143 gnd 185 data[13] 18 vdd 60 mplx_bus[20] 102 mplx_bus[7] 144 addr[14] 186 data[14] 19 gnd 61 mplx_bus[19] 103 mplx_bus[6] 145 addr[15] 187 data[15] 20 pf[7]/ int_h 62 mplx_bus[18] 104 mplx_bus[5] 146 addr[16] 188 vdd 21 pf[6] 63 gnd 105 mplx_bus[4] 147 addr[17] 189 gnd 22 pf[5] 64 vdd 106 vdd 148 addr[18] 190 data[16] 23 pf[4] 65 vdd 107 gnd 149 addr[19] 191 data[17] 24 pf[3] 66 gnd 108 mplx_bus[3] 150 vdd 192 data[18] 25 pf[2] 67 mplx_bus[17] 109 mplx_bus[2] 151 addr[20] 193 data[19] 26 pf[1] 68 mplx_bus[16] 110 mplx_bus[1] 152 addr[21] 194 data[20] 27 pf[0] 69 mplx2 111 mplx_bus[0] 153 addr[22] 195 data[21] 28 pwd 70 pci_ irdy 112 gnd 154 addr[23] 196 vdd 29 pwdack 71 vdd 113 clkout 155 addr[24] 197 gnd 30 br 72 gnd 114 vdd 156 addr[25] 198 data[22] 31 bg 73 pci_ stop 115 gnd 157 dt0 199 data[23] 32 bgh 74 mplx10 116 wr 158 tfs0 200 data[24] 33 irqe 75 mplx11 117 rd 159 rfs0 201 data[25] 34 irql0 76 pci_par 118 dmsh 160 dr0 202 data[26] 35 irql1 77 vdd 119 dmsl 161 sclk0 203 data[27] 36 irq2 78 gnd 120 pms 162 dt1 204 data[28] 37 vdd 79 mplx3 121 bms 163 tfs1 205 data[29] 38 gnd 80 mplx7 122 cms 164 rfs1 206 data[30] 39 mplx_ reset 81 mplx9 123 ioms 164 dr1 207 data[31] 40 mplx12 82 mplx8 124 vdd 166 sclk1 208 ereset 41 mplx_bus[31] 83 gnd 125 clkin 167 gnd 42 vdd 84 vdd 126 xtal 168 vdd
rev. 0 ADSP-2141L C37C pinout pci mode 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 189 188 187 186 185 184 183 182 181 180 190 179 178 177 175 174 173 172 171 170 176 169 168 167 165 164 163 162 161 160 159 158 157 166 71 72 73 74 75 76 77 78 79 80 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 81 82 83 84 86 87 88 89 90 85 91 92 93 94 96 97 98 99 95 100 101 102 103 104 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 40 39 38 37 41 43 42 45 44 50 49 48 47 46 52 51 152 153 154 155 150 151 156 148 149 143 144 145 146 141 142 140 147 138 139 134 135 136 137 132 133 130 131 128 129 125 126 127 123 124 121 122 120 117 118 119 116 114 115 112 113 107 108 109 110 111 105 106 oo mplx_bus/pci_ad[24] mplx1/pci_ cbe3 mplx_bus/pci_ad[23] mplx_bus/pci_ad[22] vdd gnd mplx_bus/pci_ad[21] mplx_bus/pci_ad[20] mplx_bus/pci_ad[20] mplx_bus/pci_ad[18] gnd vdd vdd gnd mplx_bus/pci_ad[17] mplx_bus/pci_ad[16] mplx2/pci_ cbe2 pci_ irdy vdd gnd pci_ stop mplx10/pci_p err mplx11/pci_ serr pci_par vdd gnd mplx3/pci_ cbe1 mplx7/pci_ f rame mplx9/pci_ t rdy mplx8/pci_ devsel gnd vdd vdd gnd mplx6/pci_ gnt mplx5/pci_idsel mplx_bus/pci_ad[15] mplx_bus/pci_ad[14] mplx_bus/pci_ad[13] mplx_bus/pci_ad[12] vdd gnd mplx_bus/pci_ad[11] mplx_bus/pci_ad[10] mplx_bus/pci_ad[9] mplx_bus/pci_ad[8] vdd gnd mplx4/pci_ cbe0 mplx_bus/pci_ad[7] mplx_bus/pci_ad[6] mplx_bus/pci_ad[5] pin 1 identifier top view (not to scale) ereset addr[25] addr[24] addr[23] addr[22] addr[21] addr[20] addr[19] addr[18] addr[14] addr[17] addr[16] addr[15] addr[13] addr[12] addr[11] addr[10] addr[6] addr[3] addr[2] addr[1] clkin vdd pms dmsl vdd mplx_bus/pci_ad[1] gnd vdd mplx_bus/pci_ad[4] mplx_bus/pci_ad[3] mplx_bus/pci_ad[2] mplx_bus/pci_ad[0] gnd clkout rd wr gnd dmsh bms cms xtal gnd addr[0] addr[4] addr[5] addr[7] addr[8] addr[9] vdd gnd vdd ioms ems ee gnd eclk elout elin eint ebr ebg mmap bmode bus_mode bus_sel ee_sk ee_cs ee_di ee_do vdd gnd pf[7]/ int_h pf[6] pf[5] pf[4] pf[3] pf[2] pf[1] pf[0] pwd pwdack br bg bgh irqe irql0 irql1 irq2 vdd gnd mplx_ reset /pci_ rst mplx12/pci_ req mplx_bus/pci_ad[31] vdd pci_clk gnd mplx_bus/pci_ad[30] mplx_bus/pci_ad[29] mplx_bus/pci_ad[28] mplx_bus/pci_ad[27] vdd gnd mplx_bus/pci_ad[26] mplx_bus/pci_ad[25] gnd vdd gnd vdd gnd vdd gnd vdd gnd sclk1 ADSP-2141L data[31] data[30] data[29] data[28] data[27] data[26] data[25] data[24] data[23] data[22] data[21] data[20] data[19] data[18] data[17] data[16] data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8] data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] rfs 1 tfs1 dt1 sclk0 dr0 rfs0 tfs0 dt0 pci mode dr1
rev. 0 ADSP-2141L C38C pinout 2183-mode 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 189 188 187 186 185 184 183 182 181 180 190 179 178 177 175 174 173 172 171 170 176 169 168 167 165 164 163 162 161 160 159 158 157 166 71 72 73 74 75 76 77 78 79 80 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 81 82 83 84 86 87 88 89 90 85 91 92 93 94 96 97 98 99 95 100 101 102 103 104 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 40 39 38 37 41 43 42 45 44 50 49 48 47 46 52 51 152 153 154 155 150 151 156 148 149 143 144 145 146 141 142 140 147 138 139 134 135 136 137 132 133 130 131 128 129 125 126 127 123 124 121 122 120 117 118 119 116 114 115 112 113 107 108 109 110 111 105 106 oo pin 1 identifier top view (not to scale) ee gnd eclk elout elin vdd gnd pwdack vdd gnd ems eint ebr ebg mmap bmode bus_mode bus_sel ee_sk ee_cs ee_di ee_do pf[7]/ int_h pf[6] pf[5] pf[4] pf[3] pf[2] pf[1] pf[0] pwd br bg bgh irqe irql0 irql1 irq2 mplx_ reset /reset_1 mplx12/fl2 mplx_bus/nc[31] gnd mplx_bus/nc[30] mplx_bus/nc[29] mplx_bus/nc[28] mplx_bus/nc[27] vdd gnd mplx_bus/nc[26] mplx_bus/nc[25] pci_clk vdd ADSP-2141L ereset data[31] data[30] data[29] data[28] data[27] data[26] data[25] data[24] data[23] data[22] gnd vdd data[21] data[20] data[19] data[18] data[17] data[16] gnd vdd data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8] data[7] data[6] data[5] data[4] gnd vdd data[3] data[2] data[1] data[0] gnd vdd gnd sclk1 dr1 rfs1 tfs1 dt1 sclk0 dr0 rfs0 tfs0 dt0 addr[25] addr[24] addr[23] addr[22] addr[21] addr[20] vdd addr[19] addr[18] addr[14] addr[17] addr[16] addr[15] gnd addr[13] addr[12] addr[11 ] addr[10] addr[6] addr[3] addr[2] addr[1] clkin vdd pms dmsl vdd mplx_bus/iad[1 ] gnd vdd mplx_bus/iad[4] mplx_bus/iad[3] mplx_bus/iad[2] mplx_bus/iad[0] gnd clkout wr gnd dmsh bms cms ioms xtal gnd addr[0] vdd addr[4] addr[5] addr[7] addr[8] addr[9 ] rd 2183 mode vdd gnd gnd vdd vdd gnd vdd gnd vdd gnd gnd vdd vdd gnd mplx_bus/nc[24] mplx1/nc mplx_bus/nc[23] mplx_bus/nc[22] mplx_bus/nc[21] mplx_bus/nc[20] mplx_bus/nc[19] mplx_bus/nc[18] mplx_bus/nc[17] mplx_bus/nc[16] mplx2/nc pci_ irdy pci_ stop mplx10/fl0 mplx11/fl1 pci_par mplx3/nc mplx7/is mplx9/ iack mplx8/ial mplx6/ iwr mplx5/ ird mplx_bus/iad[15] mplx_bus/iad[14] mplx_bus/iad[13] mplx_bus/iad[12] vdd gnd mplx_bus/iad[11] mplx_bus/iad[10] mplx_bus/iad[9] mplx_bus/iad[8] vdd gnd mplx4/nc mplx_bus/iad[7] mplx_bus/iad[6] mplx_bus/iad[5]
rev. 0 ADSP-2141L C39C package description package details the package shown below is a 208-lead metric quad flatpack. measurements are listed in english and (metric). because this packa ge is designed as a metric package, analog devices recommends that you use these measurements for any pcb layout. outline dimensions dimensions shown in inches and (mm). 208-lead metric plastic quad flatpack (mqfp) (nonhermetic) 1 208 157 156 105 104 53 52 top view (pins down) 0.020 (0.50) bsc 1.256 (31.40) 1.248 (31.20) sq 1.240 (31.00) 1.124 (28.10) 1.120 (28.00) sq 1.116 (27.90) 0.011 (0.27) 0.009 (0.22) 0.007 (0.17) lead pitch lead width seating plane 0.164 (4.10) max 0.003 (0.08) max lead coplanarity 0.020 (0.50) 0.010 (0.25) 0.144 (3.59) 0.136 (3.39) 10 typ 0.041 (1.03) 0.035 (0.88) 0.031 (0.78) note: the actual position of each lead is within 0.003 (0.08) from its ideal position when measured in the lateral direction. center figures are typical unless otherwise noted. the 208 lead mqfp is a metric package. english dimensions provided are approximate and must not be used for board design purposes ordering guide part number ambient temperature range instruction rate package description package option ADSP-2141Lks-n1 1 0 c to +70 c 40 mhz 208-lead mqfp s-208 ADSP-2141Lks-e1 2 0 c to +70 c 40 mhz 208-lead mqfp s-208 notes 1 the ADSP-2141Lks-n1 is an electrically equivalent, full function, production (non x-grade) version of the product described in this data sheet. (full function = triple des enabled, full 168-bit key length, full 2048-bit public key lengths, red keys allowed.) 2 the ADSP-2141Lks-e1 is an electrically equivalent, full function, production (non x-grade) version of the product d escribed in this data sheet except for the following: encryption: des only, with maximum 56-bit key length. triple des is disabled. public key algorithms: public key algorithms limited to 1024-bit max modulus. red keys not allowed in hardware crypto context. c3654C5C1/00 (rev. 0) printed in u.s.a.

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